Before the dawn of the half-submicron age, a wafer's surface flatness was a topical issue, though not an overriding one. Now, as the number of metal layers of a wafer are increasing, planarity becomes critical dimension. Today, with 0.35 micron features becoming widespread, surface planarity is assuming new importance, since it offers the key to boosting circuit performance.
Chemical mechanical polishing (CMP) is a process for improving the surface planarity of a semiconductor wafer and involves the use of mechanical pad polishing systems usually with a silica-based slurry. CMP offers a practical approach to achieving the important advantage of global wafer planarity.
However, CMP systems for global planarization have certain limitations. These limitations include low wafer throughput, polished surface non-uniformity, and a problem related to polishing uniformity known as "edge exclusion." Edge exclusion occurs when too much of the semiconductor wafer surface is polished. This causes the edge or outer portion of the wafer to be not useable for integrated circuit fabrication. Wafer polish throughput and polish uniformity are important process parameters, because they also directly affect the number of integrated circuit chips that a fabrication facility can produce per unit equipment for a given period of time.